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oki semiconductor fedl86410-01 issue date: jun. 05, 2007 ML86410 mpeg4 encoding lsi 1/27 overview the ML86410 is an lsi that encodes yuv (ycbcr) format digital video signals into mpeg-4-asp format ones in real time. the lsi achieves high picture quality by a unique high-speed high-quality motion search method and a unique coding rate control method. for video input, the lsi s upports progressive video output from camera modules and interlaced video output from ntsc /pal digital video decoders. features image encoding: ? encoding format mpeg-4 simple profile@level 3 mpeg-4 advanced simple profile@level 5 ? supported image progressive qvga, 30 fps progressive vga, 30 fps interlaced ntsc, 29.97 fps interlaced pal, 25 fps ? output frame (with a frame skipping function) qvga/ vga : 30/15/1/0.5 fps ntsc : 29.97/14.985/0.999/0.4995 fps pal : 25/12.5/1/0.5 fps ? coding type iiii ippp ? encoding mode cbr (up to 6 mbps) vbr ? supports interlaced images (ntsc/pal) ? unique high-speed high-quality motion search method ? unique coding rate control method ? 4mv motion estimation ? detectes abnormality such as: camera input abnormality stream data readout abnormality set bit rate exceeded ? can suspend/restart encoding free datasheet http:///
fedl86410-01 oki semiconductor ML86410 2/27 video interface: ? qvga (320 240 pixels) / vga (640 480 pixels) : ycbcr (8-bit (ycbcr) (4:2:2) ) + sync, 27 mhz yuv (8-bit (yuv)(4:2:2)) + sync, 27 mhz ? ntsc (720 480 pixels) ) / pal (720 576 pixels) : itu-r bt.656, 27 mhz note: although signals are input in 4:2:2 format, they are converted to 4:2:0 format before encoding processing. ? can choose the order in which fields are load ed during interlacing (top first/bottom first) ? can choose between the positive polarity and the negative polarity of clkcam when loading yuvdata, vsync, or hsync ? clipping can be specified as no clipping or clipping in the range of 16 y,u,v 240 ? for the interface, a 3.3 v i/o interface is used. host cpu interface: ? general-purpose 8-/16-bit data bus (can be connect ed directly with oki?s arm microcontroller series) ? operable as an i/o device in dma mode from the host cpu external sdram interface: ? 32-bit data bus, 2 mwords 32 bits, 81 mhz (equivalent to pc133) ? automatic initialization sequence ? column address: 8/9/10 bits selectable input clock: ? system clock : 27 mhz ? video interface : 27 mhz power management: ? no power management function is provided power supply voltage: ? core section : 1.35 to 1.65 v ? i/o section : 3.0 to 3.6 v ? pll section : 1.35 to 1.65 v operating frequency: ? internal : 81 mhz ? video interface section : 27 mhz operating temperature (ambient temperature): ? -20 to +85c package: ? 144-pin plastic lqfp (lqfp144-p-2020-0.50-zk) free datasheet http:///
fedl86410-01 oki semiconductor ML86410 3/27 block diagram figure 1-1 shows the block diagram of the ML86410. host cpu hsync, vsync video clock 32-bit sdram 8-/16-bit data a ddress cs, we wait video i/f mpeg-4 encoder host cpu i/f dram i/f pll yuv 8-bit osc interrupt dack dreq reset camera ML86410 figure 1 block diagram free datasheet http:///
fedl86410-01 oki semiconductor ML86410 4/27 pin configuration figure 1-2 shows the pin configuration of the 144-pin lqfp. gndio sddata22 sddata21 sddata20 vddcore gndcore sddata19 sddata18 sddata17 sddata16 sddata15 sddata14 sddata13 gndio sddata12 vddio vddcore sddata11 sddata10 gndcore sddata9 sddata8 sddata7 sddata6 sddata5 sddata4 vddcore sddata3 sddata2 sddata1 gndcore sddata0 vddio sdclk gndio sdadrs12 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 vddi o 109 72 sdadrs11 s ddata23 110 71 sdadrs10 s ddata24 111 70 sdadrs9 s ddata25 112 69 vddcore s ddata26 113 68 gndcore s ddata27 114 67 sdadrs8 vdd co re 115 66 sdadrs7 s ddata28 116 65 sdadrs6 s ddata29 117 64 sdadrs5 g nd co re 118 63 sdadrs4 s ddata30 119 62 sdadrs3 s ddata31 120 61 sdadrs2 s d c ke 121 60 sdadrs1 s d cs n 122 59 sdadrs0 s dra s n 123 58 vddio s d c a s n 124 57 gndcore s dwen 125 56 intn s dd q m 126 55 dack g ndi o 127 54 dreq c lk c am 128 53 xwait g nd co re 129 52 gndio vdd co re 130 51 xren yuvdata0 131 50 vddcore yuvdata1 132 49 xwen yuvdata2 133 48 vddio yuvdata3 134 47 xcsn yuvdata4 135 46 gndcore yuvdata5 136 45 xd15 yuvdata6 137 44 xd14 yuvdata7 138 43 vddcore v s yn c 139 42 xd13 h s yn c 140 41 xd12 g nd co re 141 40 xd11 n c 142 39 xd10 vdd co re 143 38 xd9 fieldt o p 144 37 xd8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 vddpll gndpll gndio xi xo vddio gndcore vddcore tmode0 tmode1 tmode2 gndio rstn vddio xa0 xa1 xa2 xa3 xa4 xa5 xa6 xa7 xa8 gndcore xa9 vddcore xd0 xd1 xd2 xd3 xd4 xd5 gndcore vddcore xd6 xd7 lqfp144-p-2020-0.50-zk figure 2 144-pin lqfp pin configuration free datasheet http:///
fedl86410-01 oki semiconductor ML86410 5/27 list of pins pin no. symbol i/o description 1 vddpll vdd pll power supply 2 gndpll gnd pll gnd 3 gndio gnd i/o gnd 4 xi ? input clock (27 mhz) 5 xo ? input clock (27 mhz) 6 vddio vdd i/o power supply 7 gndcore gnd core gnd 8 vddcore vdd core power supply 9 tmode0 i test mode 0 10 tmode1 i test mode 1 11 tmode2 i test mode 2 12 gndio gnd i/o gnd 13 rstn i reset 14 vddio vdd i/o power supply 15 xa0 i external bus address input signal 0 16 xa1 i external bus address input signal 1 17 xa2 i external bus address input signal 2 18 xa3 i external bus address input signal 3 19 xa4 i external bus address input signal 4 20 xa5 i external bus address input signal 5 21 xa6 i external bus address input signal 6 22 xa7 i external bus address input signal 7 23 xa8 i external bus address input signal 8 24 gndcore gnd core gnd 25 xa9 i external bus address input signal 9 26 vddcore vdd core power supply 27 xd0 i/o external bus input/output data 0 28 xd1 i/o external bus input/output data 1 29 xd2 i/o external bus input/output data 2 30 xd3 i/o external bus input/output data 3 31 xd4 i/o external bus input/output data 4 32 xd5 i/o external bus input/output data 5 33 gndcore gnd core gnd 34 vddcore vdd core power supply 35 xd6 i/o external bus input/output data 6 36 xd7 i/o external bus input/output data 7 37 xd8 i/o external bus input/output data 8 38 xd9 i/o external bus input/output data 9 39 xd10 i/o external bus input/output data 10 40 xd11 i/o external bus input/output data 11 41 xd12 i/o external bus input/output data 12 42 xd13 i/o external bus input/output data 13 43 vddcore vdd core power supply 44 xd14 i/o external bus input/output data 14 45 xd15 i/o external bus input/output data 15 46 gndcore gnd core gnd 47 xcsn i chip enable signal free datasheet http:///
fedl86410-01 oki semiconductor ML86410 6/27 pin no. symbol i/o description 48 vddio vdd i/o power supply 49 xwen i write enable signal 50 vddcore vdd core power supply 51 xren i read enable signal 52 gndio gnd i/o gnd 53 xwait o wait signal 54 dreq o dma request 55 dack i dma acknowledge 56 intn o interrupt signal output 57 gndcore gnd core gnd 58 vddio vdd i/o power supply 59 sdadrs0 o sdram address 0 60 sdadrs1 o sdram address 1 61 sdadrs2 o sdram address 2 62 sdadrs3 o sdram address 3 63 sdadrs4 o sdram address 4 64 sdadrs5 o sdram address 5 65 sdadrs6 o sdram address 6 66 sdadrs7 o sdram address 7 67 sdadrs8 o sdram address 8 68 gndcore gnd core gnd 69 vddcore vdd core power supply 70 sdadrs9 o sdram address 9 71 sdadrs10 o sdram address 10 72 sdadrs11 o sdram address 11 73 sdadrs12 o sdram address 12 74 gndio gnd i/o gnd 75 sdclk o sdram clock 76 vddio vdd i/o power supply 77 sddata0 i/o sdram data 0 78 gndcore gnd core gnd 79 sddata1 i/o sdram data 1 80 sddata2 i/o sdram data 2 81 sddata3 i/o sdram data 3 82 vddcore vdd core power supply 83 sddata4 i/o sdram data 4 84 sddata5 i/o sdram data 5 85 sddata6 i/o sdram data 6 86 sddata7 i/o sdram data 7 87 sddata8 i/o sdram data 8 88 sddata9 i/o sdram data 9 89 gndcore gnd core gnd 90 sddata10 i/o sdram data 10 91 sddata11 i/o sdram data 11 92 vddcore vdd core power supply 93 vddio vdd i/o power supply 94 sddata12 i/o sdram data 12 95 gndio gnd i/o gnd 96 sddata13 i/o sdram data 13 97 sddata14 i/o sdram data 14 free datasheet http:///
fedl86410-01 oki semiconductor ML86410 7/27 pin no. symbol i/o description 98 sddata15 i/o sdram data 15 99 sddata16 i/o sdram data 16 100 sddata17 i/o sdram data 17 101 sddata18 i/o sdram data 18 102 sddata19 i/o sdram data 19 103 gndcore gnd core gnd 104 vddcore vdd core power supply 105 sddata20 i/o sdram data 20 106 sddata21 i/o sdram data 21 107 sddata22 i/o sdram data 22 108 gndio gnd i/o gnd 109 vddio vdd i/o power supply 110 sddata23 i/o sdram data 23 111 sddata24 i/o sdram data 24 112 sddata25 i/o sdram data 25 113 sddata26 i/o sdram data 26 114 sddata27 i/o sdram data 27 115 vddcore vdd core power supply 116 sddata28 i/o sdram data 28 117 sddata29 i/o sdram data 29 118 gndcore gnd core gnd 119 sddata30 i/o sdram data 30 120 sddata31 i/o sdram data 31 121 sdcke o sdram cke pin control (clock enable) 122 sdcsn o sdram cs pin control (chip select) 123 sdrasn o sdram ras pin control (row address strobe) 124 sdcasn o sdram cas pin control (column address strobe) 125 sdwen o sdram we pin control (write enable) 126 sddqm o sdram dqm pin control (dq mask) 127 gndio gnd i/o gnd 128 clkcam i pixel clock 129 gndcore gnd core gnd 130 vddcore vdd core power supply 131 yuvdata0 i yuv data input 0 132 yuvdata1 i yuv data input 1 133 yuvdata2 i yuv data input 2 134 yuvdata3 i yuv data input 3 135 yuvdata4 i yuv data input 4 136 yuvdata5 i yuv data input 5 137 yuvdata6 i yuv data input 6 138 yuvdata7 i yuv data input 7 139 vsync i vertical sync signal 140 hsync i horizontal sync signal 141 gndcore gnd core gnd 142 nc i unused pin 143 vddcore vdd core power supply 144 fieldtop i field signal free datasheet http:///
fedl86410-01 oki semiconductor ML86410 8/27 pin description pin no. symbol i/o descripti on at reset active level type of i/o drive performa nce sdram interface (52 pins) 75 sdclk out sdram clock low ? 6 ma 59 sdadrs0 out sdram address 0 low ? 4 ma 60 sdadrs1 out sdram address 1 low ? 4 ma 61 sdadrs2 out sdram address 2 low ? 4 ma 62 sdadrs3 out sdram address 3 low ? 4 ma 63 sdadrs4 out sdram address 4 low ? 4 ma 64 sdadrs5 out sdram address 5 low ? 4 ma 65 sdadrs6 out sdram address 6 low ? 4 ma 66 sdadrs7 out sdram address 7 low ? 4 ma 67 sdadrs8 out sdram address 8 low ? 4 ma 70 sdadrs9 out sdram address 9 low ? 4 ma 71 sdadrs10 out sdram address 10 low ? 4 ma 72 sdadrs11 out sdram address 11 low ? 4 ma 73 sdadrs12 out sdram address 12 low ? 4 ma 77 sddata0 in/out sdram data 0 hi-z ? pull-down 4 ma 79 sddata1 in/out sdram data 1 hi-z ? pull-down 4 ma 80 sddata2 in/out sdram data 2 hi-z ? pull-down 4 ma 81 sddata3 in/out sdram data 3 hi-z ? pull-down 4 ma 83 sddata4 in/out sdram data 4 hi-z ? pull-down 4 ma 84 sddata5 in/out sdram data 5 hi-z ? pull-down 4 ma 85 sddata6 in/out sdram data 6 hi-z ? pull-down 4 ma 86 sddata7 in/out sdram data 7 hi-z ? pull-down 4 ma 87 sddata8 in/out sdram data 8 hi-z ? pull-down 4 ma 88 sddata9 in/out sdram data 9 hi-z ? pull-down 4 ma 90 sddata10 in/out sdram data 10 hi-z ? pull-down 4 ma 91 sddata11 in/out sdram data 11 hi-z ? pull-down 4 ma 94 sddata12 in/out sdram data 12 hi-z ? pull-down 4 ma 96 sddata13 in/out sdram data 13 hi-z ? pull-down 4 ma 97 sddata14 in/out sdram data 14 hi-z ? pull-down 4 ma 98 sddata15 in/out sdram data 15 hi-z ? pull-down 4 ma 99 sddata16 in/out sdram data 16 hi-z ? pull-down 4 ma 100 sddata17 in/out sdram data 17 hi-z ? pull-down 4 ma 101 sddata18 in/out sdram data 18 hi-z ? pull-down 4 ma 102 sddata19 in/out sdram data 19 hi-z ? pull-down 4 ma 105 sddata20 in/out sdram data 20 hi-z ? pull-down 4 ma 106 sddata21 in/out sdram data 21 hi-z ? pull-down 4 ma 107 sddata22 in/out sdram data 22 hi-z ? pull-down 4 ma 110 sddata23 in/out sdram data 23 hi-z ? pull-down 4 ma 111 sddata24 in/out sdram data 24 hi-z ? pull-down 4 ma 112 sddata25 in/out sdram data 25 hi-z ? pull-down 4 ma 113 sddata26 in/out sdram data 26 hi-z ? pull-down 4 ma 114 sddata27 in/out sdram data 27 hi-z ? pull-down 4 ma 116 sddata28 in/out sdram data 28 hi-z ? pull-down 4 ma 117 sddata29 in/out sdram data 29 hi-z ? pull-down 4 ma free datasheet http:///
fedl86410-01 oki semiconductor ML86410 9/27 pin no. symbol i/o descripti on at reset active level type of i/o drive performa nce 119 sddata30 in/out sdram data 30 hi-z ? pull-down 4 ma 120 sddata31 in/out sdram data 31 hi-z ? pull-down 4 ma 121 sdcke out sdram cke pin control (clock enable) high high 4 ma 122 sdcsn out sdram cs pin control (chip select) high low 4 ma 123 sdrasn out sdram ras pin control (row address strobe) high low 4 ma 124 sdcasn out sdram cas pin control (column address strobe) high low 4 ma 125 sdwen out sdram we pin control (write enable) high low 4 ma 126 sddqm out sdram dqm pin control (dq mask) high high 4 ma video interface (12 pins) 131 yuvdata0 in yuv data input 0 ? high ? 132 yuvdata1 in yuv data input 1 ? high ? 133 yuvdata2 in yuv data input 2 ? high ? 134 yuvdata3 in yuv data input 3 ? high ? 135 yuvdata4 in yuv data input 4 ? high ? 136 yuvdata5 in yuv data input 5 ? high ? 137 yuvdata6 in yuv data input 6 ? high ? 138 yuvdata7 in yuv data input 7 ? high ? 139 vsync in vertical sync signal ? high ? 140 hsync in horizontal sync signal ? high ? 144 fieldtop in field signal by interlacing 0 : bottom field 1 : top field ? high ? 128 clkcam in pixel clock ? high schmitt ? host cpu interface (33 pins) 15 xa0 in external bus address output signal 0 ? ? ? 16 xa1 in external bus address output signal 1 ? ? ? 17 xa2 in external bus address output signal 2 ? ? ? 18 xa3 in external bus address output signal 3 ? ? ? 19 xa4 in external bus address output signal 4 ? ? ? 20 xa5 in external bus address output signal 5 ? ? ? 21 xa6 in external bus address output signal 6 ? ? ? 22 xa7 in external bus address output signal 7 ? ? ? 23 xa8 in external bus address output signal 8 ? ? ? free datasheet http:///
fedl86410-01 oki semiconductor ML86410 10/27 pin no. symbol i/o descripti on at reset active level type of i/o drive performa nce 25 xa9 in external bus address output signal 9 ? ? ? 27 xd0 in/out external bus input/output data 0 hi-z ? 4 ma 28 xd1 in/out external bus input/output data 1 hi-z ? 4 ma 29 xd2 in/out external bus input/output data 2 hi-z ? 4 ma 30 xd3 in/out external bus input/output data 3 hi-z ? 4 ma 31 xd4 in/out external bus input/output data 4 hi-z ? 4 ma 32 xd5 in/out external bus input/output data 5 hi-z ? 4 ma 35 xd6 in/out external bus input/output data 6 hi-z ? 4 ma 36 xd7 in/out external bus input/output data 7 hi-z ? 4 ma 37 xd8 in/out external bus input/output data 8 hi-z ? 4 ma 38 xd9 in/out external bus input/output data 9 hi-z ? 4 ma 39 xd10 in/out external bus input/output data 10 hi-z ? 4 ma 40 xd11 in/out external bus input/output data 11 hi-z ? 4 ma 41 xd12 in/out external bus input/output data 12 hi-z ? 4 ma 42 xd13 in/out external bus input/output data 13 hi-z ? 4 ma 44 xd14 in/out external bus input/output data 14 hi-z ? 4 ma 45 xd15 in/out external bus input/output data 15 hi-z ? 4 ma 47 xcsn in chip enable signal ? low ? 49 xwen in write enable signal ? low ? 51 xren in read enable signal ? low ? 53 xwait out wait signal low high 4 ma 54 dreq out dma request 0/1= no request / request low high 4 ma 55 dack in dma acknowledge 0/1= no clear / clear connect this pin to gnd when performing program transfer using the dma signal control register. ? high pull-down ? 56 intn out interrupt signal output high low 2 ma free datasheet http:///
fedl86410-01 oki semiconductor ML86410 11/27 pin no. symbol i/o descripti on at reset active level type of i/o drive performa nce clock/reset (3 pins) 13 rstn in reset 0: active ? low schmitt, pull-up ? 4 xi ? input clock (27 mhz) ? ? ? 5 xo ? input clock (27 mhz) ? ? ? test mode related (3 pins) 9 tmode0 in test mode signal 0 ? ? schmitt, pull-down ? 10 tmode1 in test mode signal 1 ? ? schmitt, pull-down ? 11 tnode2 in test mode signal 2 ? ? schmitt, pull-down ? unused signal (1 pin) 142 nc in unused pin connect this pin to gnd. ? ? ? power supply/gnd (40 pins) 6,14,48, 58,76,93, 109 vddio in digital power supply (i/o) ? ? ? 3,12, 52, 74, 95, 108, 127 gndio in digital gnd (i/o) ? ? ? 8, 26, 34, 43, 50, 69, 82, 92, 104,115, 130, 143 vddcore in digital power supply (core) ? ? ? 7, 24, 33, 46, 57, 68, 78, 89, 103, 118, 129, 141 gndcore in digital gnd (core) ? ? ? 1 vddpll in analog (pll) power supply ? ? ? 2 gndpll in analog (pll) gnd ? ? ? free datasheet http:///
fedl86410-01 oki semiconductor ML86410 12/27 absolute maximum ratings table 1 absolute maximum ratings parameter symbol condition rating unit digital power supply voltage (core) v ddcore ? (*1) ?0.3 to +2.0 digital power supply voltage (i/o) v ddio ? (*1) ?0.3 to +4.6 pll power supply voltage v ddpll ? (*1) ?0.3 to +2.0 input voltage (normal buffer) v i ? (*1) ?0.3 to v ddio +0.3 output voltage (normal buffer) v o ? (*1) ?0.3 to v ddio +0.3 v allowable input current i i ? (*1) ?10 to +10 allowable output current (2 ma buffer) ?8 to +8 allowable output current (4 ma buffer) ?16 to +16 allowable output current (6 ma buffer) i o ? (*1) ?24 to +24 ma power dissipation p d ta = 85c 1450 mw storage temperature t stg ? ?50 to +150 c *1: the gnd pins are at 0 v when ta = 25c recommended operating conditions table 2 recommended operating conditions parameter symbol conditio n min. typ. max. unit digital power supply voltage (core) v ddcore 1.35 1.5 1.65 digital power supply voltage (i/o) v ddio v ddio v ddcore 3.0 3.3 3.6 pll power supply voltage v ddpll 1.35 1.5 1.65 v operating frequency f op ? ? 81 mhz ambient temperature ta ? -20 25 85 c free datasheet http:///
fedl86410-01 oki semiconductor ML86410 13/27 dc characteristics table 3 dc characteristics (v ddcore = 1.35 to 1.65 v, v ddio = 3.0 to 3.6 v, ta = -20 to +85c) parameter symbol condition min. typ. max. unit input ?h? voltage (normal pins) v ih1 applied to normal pins 2.0 ? v ddio +0.3 input ?l? voltage (normal pins) v il1 applied to normal pins ?0.3 ? 0.8 v t+ ? ? ? 2.1 v t- ? 0.7 ? ? ttl level schmitt trigger input threshold voltage ? v t v t+ ? v t- 0.25 ? ? output ?h? voltage v oh1 v ddio = 3.0 to 3.6 v applied to normal pins 2.4 ? ? output ?l? voltage v ol1 v ddio = 3.0 to 3.6 v applied to normal pins ? ? 0.4 v input leakage current 1 i il1 v i = 0v / v ddio applied to normal pins ?10 ? 10 input leakage current 2 i il2 vi = 0 v applied to pins pulled up with 50 k ? ?200 ? -10 input leakage current 3 i il3 vi = v ddio applied to pins pulled down with 50 k ? 10 ? 200 a input pin capacitance c i ? ? 5 ? output pin capacitance c o ? ? 5 ? input/output pin capacitance c io ? ? 5 ? pf chip power consumption (operating) p total ? 250 ? mw io supply current (operating) i ddoio ? 30 ? ma core and pll supply current (operating) i ddocore v ddcore = 1.5 v, v ddio = 3.3 v, ta = 25c ? 100 ? ma io supply current (standby) i ddsio ? 1 ? ua core and pll supply current (standby) i ddcore v ddcore = 1.5 v, v ddio = 3.3 v, ta = 25c ? 2 ? ma free datasheet http:///
fedl86410-01 oki semiconductor ML86410 14/27 ac characteristics reset timing table 4 reset timing (v ddcore = 1.35 to 1.65 v, v ddio = 3.0 to 3.6 v, ta = -20 to +85c) parameter symbol condition min. typ. max. unit reset pulse width t rstw ? 11 ? ? ms ?rstn? t rstw figure 3 reset timing clock timing (xi, xo) table 5 clock timing (v ddcore = 1.35 to 1.65 v, v ddio = 3.0 to 3.6 v, ta = -20 to +85c) parameter symbol condition min. typ. max. unit clock (clk) frequency f clk ? ? 27.0 ? mhz clock (clk) cycle t clk ? ? 1/f clk ? s clk t clk = 1/f clk figure 4 clock timing free datasheet http:///
fedl86410-01 oki semiconductor ML86410 15/27 external sdram timing table 6 external sdram timing (v ddcore = 1.35 to 1.65 v, v ddio = 3.0 to 3.6 v, ta = -20 to +85c) sdram parameter symbol condition min. typ. max. unit remarks sdclk cycle t sdc ? t clk / 3 ? cs output delay time t sdcsd 0.5t sdc ? 3.0 ? 0.5t sdc + 4.5 dqm output delay time t sddqmd 0.5t sdc ? 3.0 ? 0.5t sdc + 4.5 ras output delay time t sdrasd 0.5t sdc ? 3.0 ? 0.5t sdc + 4.5 cas output delay time t sdrasd 0.5t sdc ? 3.0 ? 0.5t sdc + 4.5 we output delay time t sdwed 0.5t sdc ? 3.0 ? 0.5t sdc + 4.5 sdadrs[12:0] output delay time t sdxad 0.5t sdc ? 3.0 ? 0.5t sdc + 4.5 sddata[31:0] output delay time t sdxdod 0.5t sdc ? 3.0 ? 0.5t sdc + 4.5 sddata[31:0] output hold time t sdxdoh 0.5t sdc ? 3.0 ? ? sddata[31:0] output enable time t sdxdoe 0.5t sdc ? 3.0 ? 0.5t sdc + 4.5 sddata[31:0] output disable time t sdxdode 0.5t sdc ? 3.0 ? ? sddata[31:0] input setup time t sdxdis 2 ? ? sddata[31:0] input hold time t sdxdih cl = 20 pf 4.5 ? ? (81 mhz) minimum delay time, ras to cas t sdrcd n sd1 x t sdc ? ? n sd1 = trcd=2 ras active time t sdras n sd2 x t sdc ? ? n sd2 = tras=5 ras precharge time t sdrp ? n sd3 x t sdc ? ? ns n sd3 = trp=2 note : t clk =1/ f clk (f clk =27mhz) free datasheet http:///
fedl86410-01 oki semiconductor ML86410 16/27 external sdram read timing (32- bit bus width sd ram word access) sdcl k sdras n sdwe n sddata31 to sddata 0 sdcs n sdcas n sddq m sdadrs1 2 to sdadrs 0 t sdxad t sdcsd t sdrasd t sdrasd t sdcasd t sdcasd t sddqmd t sddqmd t sdwed t sdxdis t sdxdih t sdras t sdrp t sdrcd t sdcsd t sdwed d1-1 ra1 ca1 t sdxad t sdxad t sdxad t sdrasd t sdrasd t sdcsd t sdcsd t sdcsd t sdcsd t sdcsd sdck e t sdrasd t sdc figure 5 external sdram read timing free datasheet http:///
fedl86410-01 oki semiconductor ML86410 17/27 external sdram write timi ng (32-bit bus width sdra m byte/half-word access) sdcl k sdrasn sdwe n sddata31 to sddata0 sdcs n sdcas n sddq m sdadrs12 to sdadrs0 t sdxad t sdcsd t sdrasd t sdrasd t sdcasd t dqmd t sdwed t sdrp t sdras t sdrcd t sdxdoe t sdxdod t sdxdoh t sdxdode t sdcsd t sdcasd t dqmd t sdwed d1-1 ra1 ca1 t sdxad t sdxad t sdxad t sdcsd t sdcsd t sdcsd t sdcsd t sdrasd t sdrasd t sdwed t sdwed sdck e t sdcsd t sdrasd figure 6 external sdram write timing free datasheet http:///
fedl86410-01 oki semiconductor ML86410 18/27 video interface timing table 7 video interface timing (v ddcore = 1.35 to 1.65 v, v ddio = 3.0 to 3.6 v, ta = -20 to +85c) parameter symbol condition min. typ. max. unit remarks clkcam frequency f clkcam ? 27 ? mhz clkcam cycle t clkcam ? 1/f clkcam ? s clkcam input setup time t svi 10 ? ? clkcam input hold time t hvi cl = 20 pf 5 ? ? ns capture clock edge setting: positive clkcam t svi vsync hsync fieldtop yuvdata7 to yuvdata0 t shi t clkcam capture clock edge setting: negative clkcam t svi vsync hsync fieldtop yuvdata7 to yuvdata0 t shi t clkcam figure 7 video interface timing free datasheet http:///
fedl86410-01 oki semiconductor ML86410 19/27 host cpu interface timing table 8 host cpu interface timing (v ddcore = 1.35 to 1.65 v, v ddio = 3.0 to 3.6 v, ta = -20 to +85c) parameter symbol condition min. typ. max. unit remarks system clock period t hclk ? ? t clk / 3 ? ns the signal internal to the lsi (81 mhz) xcsn access time t xcs 5t hclk + 5.0 ? ? xa access time t xa 5t hclk + 5.0 ? ? xren access time t xrew t xwaitrd + t xwaitrw + 5.0 ? ? xren input setup time 1 t xcsris 5.0 ? ? xren input setup time 2 t xaris 5.0 ? ? xren input hold time 1 t xcsrih 5.0 ? ? xren input hold time 2 t xarih 5.0 ? ? xren invalid time t xreinvalid 2t hclk + 5.0 ? ? xwen access time t xwew t xwaitwd + t xwaitww + 5.0 ? ? xwen input setup time 1 t xcswis 5.0 ? ? xwen input setup time 2 t xawis 5.0 ? ? xwen input hold time 1 t xcswih 5.0 ? ? xwen input hold time 2 t xawih 5.0 ? ? xwen invalid time t xweinvalid 2t hclk + 5.0 ? ? xwait output delay time (read access) t xwaitrd 0.0 ? 10.0 xwait output delay time (write access) t xwaitwd 0.0 ? 10.0 xwait output time (read access) t xwaitrw 4t hclk ? 7t hclk xwait output time (write access) t xwaitww 4t hclk ? 7t hclk xd output setup time t xdos t hclk ? 2.0 ? ? xd output hold time t xdoh 1.5 ? 10.0 xd input setu p time t xdis 5.0 ? ? xd input hold time t xdih cl = 40 pf 5.0 ? t hclk ns note : t clk =1/ f clk (f clk =27mhz) free datasheet http:///
fedl86410-01 oki semiconductor ML86410 20/27 read cycle (read access from host cpu to ML86410) xa9 to xa0 xcsn xren xwait xd15 to dx0 valid valid t xcsris t xaris t xcsrih t xarih t xw aitrd t xwaitrw t xdos t xdoh t xreinvalid t xcs t xa t xrew hclk(*) t hclk * the signal internal to the lsi figure 8 host cpu interface timing (read cycle) free datasheet http:///
fedl86410-01 oki semiconductor ML86410 21/27 write cycle (write cycle fr om host cpu to ML86410) xa9 to xo0 xcsn xwen xwait xd15 to xd0 valid valid t xcswis t xawis t xcswih t xawih t xwaitwd t xwaitww t xweinvalid t xcs t xa t xwew t xdis t xdih figure 9 host cpu interface timing (write cycle) free datasheet http:///
fedl86410-01 oki semiconductor ML86410 22/27 dma signal timing table 9 dma signal timing (v ddcore = 1.35 to 1.65 v, v ddio = 3.0 to 3.6 v, ta = -20 to +85c) parameter symbol condition min. typ. max. unit remarks system clock period t hclk ? ? t clk / 3 ? ns the signal internal to the lsi (81 mhz) dreq positive period t dreqpos cl=20pf 4t hclk - - ns dreq negative period t dreqneg cl=20pf 3t hclk - - ns dreq deassert delay t dreqdd cl=20pf 3t hclk - 5t hclk ns this maximum value is a value when dack is asserted after the dma read access by this lsi is completed. when dack is asserted before the access is completed, the dreq deassert delay increases. dreq assert delay t dreqad cl=20pf 3t hclk - - ns dack positive period t dackpos cl=20pf 3t hclk - - ns dack negative period t dackneg cl=20pf 3t hclk - - ns dack deassert delay t dackdd cl=20pf 0t hclk - - ns dack assert delay t dackad cl=20pf 0t hclk - - ns note : t clk =1/ f clk (f clk =27mhz) free datasheet http:///
fedl86410-01 oki semiconductor ML86410 23/27 figure 10 dma signal timing [1]: after the data transfer, the samp le does dack to this lsi. if dack is high-level, dreq is deasserted. it is waited to become high-level if it is a low-level. this lsi operates recognizing the signal level of dack. [2]:after the dreq is deasserted , this lsi waits for dack to become a low-level. when the dack is low-level , the next stream data is transmitted. note: in the ac characteristics timing diagrams shown in this section, the intervals are measured at the 1/2 v ddio on the input and output waveforms. dreq dack t dreqdd t dreqad t dreqpos t dreqneg t dackpos t dackneg t dackad t dackdd [1] [2] free datasheet http:///
fedl86410-01 oki semiconductor ML86410 24/27 application example ethernet camera system ML86410 host cpu sdram 2mwx32bits flash mac phy lan mic speaker camera module osc 27mhz audio codec osc free datasheet http:///
fedl86410-01 oki semiconductor ML86410 25/27 package dimensions lqfp144-p-2020-0.50-zk package material epoxy resin lead frame material cu alloy lead finish sn / 1 to 3bi pin treatment solder plating ( 5m) package weight (g) 1.29 typ. 5 rev. no./last revised 3/nov. 15, 2004 notes for mounting the surfa ce mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humid ity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). free datasheet http:///
fedl86410-01 oki semiconductor ML86410 26/27 revision history page document no. date previous edition current edition description pedl86410-01 oct.27,2006 ? ? preliminary edition 1 ( this edition is not official.) pedl86410-16 dec.20,2006 ? ? preliminary edition 16 ( same as japanese 16th edition ) fedl86410-01 jun.05,2007 ? 1 ? 1 final edition 1 changed into "ippp" from "ippp" of the coding type in 1.1 features. free datasheet http:///
fedl86410-01 oki semiconductor ML86410 27/27 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. wh en planning to use the product, please ensure that the external conditions are reflected in the act ual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including , but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, impr oper installation, repair, alteratio n or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifi cally authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or appli cation may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, tra ffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of de termining the legality of export of these products and will take appropriate and necessary st eps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2007 oki electric industry co., ltd. free datasheet http:///

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